As each Compute Unit has a limited number of VGPRs available to it by design, how many batches the GPU can schedule to it depends on the number of VGPRs used by the shader. That is something that is determined during compilation. How many batches the GPU can preassign depends on the number of vector registers (VGPRs) the shader declares it needs for its execution. Because stalls are common, the GPU preemptively prepares a buffer of batches and assigns them to each of the Compute Units (that do the execution) ready to be used. To avoid wasting time waiting, the GPU will try to find some other work to do by swapping the now stalled batch (warp/wavefront) with another one, to execute another instruction. This is a stalling instruction meaning that the GPU must wait until the data is available (so to summarise, the GPU stalls when using the data, not when requesting it). Just before that it will insert a wait instruction to make sure that the data has arrived. At some point, towards the end of the program, it will need to actually use the uvScale. The GPU will issue the texture load towards the beginning of the program and then continue executing instructions. I have annotated with the same colour instructions in the shader and the corresponding instruction in the ISA code.
This is compiled to the following ISA s_swappc_b64 s, s Result.position = mul(WorldViewProjection, float4(, 1)) As an example check the following semi fictional shader, in which we do some Maths and read a uvScale from a texture: Texture1D Materials : register(t0) If the data is ready it uses it, if not it needs to stop execution to wait for it. When it needs to use the data it stops to check if it is available. asks for the data) and continues to execute instructions following it in the shader program. When it comes across a memory instruction the GPU issues it (i.e. This latency has the potential to stall the GPU while waiting for the data. the time between issuing the instruction and getting the result back is long), due to having to reach out to caches and maybe RAM to fetch data. Typically, instructions that fetch data from memory have a lot of latency (i.e.
I had a good question through Twitter DMs about what occupancy is and why is it important for shader performance, I am expanding my answer into a quick blog post.įirst some context, GPUs, while running a shader program, batch together 64 or 32 pixels or vertices (called wavefronts on AMD or warps on NVidia) and execute a single instruction on all of them in one go.
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